Not Applicable.
Not Applicable.
The present embodiments relate to electronic circuits and are more particularly directed to electronic circuit transistors having source/drain extensions.
Semiconductor devices are prevalent in all aspects of electronic circuits, and the design of such circuits often involves a choice from various circuit elements such as one or more different transistor devices. For example, in various applications including many high performance applications, transistors are formed with regions that are sometimes referred to either as drain extensions or source/drain extensions, where either name is used because the region extends the source/drain of the transistor to the area under the transistor gate. Several years ago such extensions were formed in some applications using xe2x80x9clightly-doped drainxe2x80x9d extensions, typically identified with the abbreviation LDD. More recently, a comparable structure also extending under the gate channel has been formed, but the amount of dopant concentration in what formerly were the LDD extensions has increased. As a result, these regions are more recently referred to as HDD extensions due to the higher dopant concentration. For the sake of a consistent explanation in this document, all such regions will be referred to generally as source/drain extensions.
By way of further background, the following Figures and discussion illustrate one prior art approach for forming a MOS transistor that includes source/drain extensions, and by way of example a PMOS transistor is shown with it understood that various comparable aspects may implemented with respect to an NMOS transistor. Looking to FIG. 1a, it illustrates a cross-sectional view of a prior art integrated circuit semiconductor device designated generally at 10 and which is built in connection with a substrate 12. By way of example, substrate 12 is a p-type semiconductor material with an n-type well 12xe2x80x2 formed in substrate 12. Relative to n-type well 12xe2x80x2 (and substrate 12), a gate stack 14 is formed with a gate insulator 16 separating a gate 18 from n-type well 12xe2x80x2. Generally, gate stack 14 is etched from a stack of layers (not shown) formed over n-type well 12xe2x80x2 that include an oxide layer adjacent pntype well 12xe2x80x2 and a polysilicon layer adjacent the oxide layer. Typically, when gate stack 14 is etched through those layers, most or all of the oxide layer is removed outside of the area of gate stack 14. Thereafter, a first insulating layer 20 is formed over gate stack 14, where first insulating layer 20 is typically oxide. Next, a p-type (e.g., boron) dopant implant is performed into device 10. As a result, this p-type implant forms source/drain extensions 221 and 222 within n-type well 12xe2x80x2 and self-aligned with respect to the thickness of insulating layer 20 where it is along the sidewalls of gate 18.
FIG. 1b illustrates device 10 after the formation steps shown in FIG. 1a, and additionally in FIG. 1b a first anneal is performed. The annealing step activates the dopants in source/drain extensions 221 and 222 shown in FIG. 1a, and this annealing thereby causes the dopants in those extensions to migrate laterally; thus, in FIG. 1b, source/drain extensions 221 and 222 from FIG. 1a are labeled 221xe2x80x2 and 222xe2x80x2 so as to distinguish them from their form prior to the anneal. Note that source/drain extensions 221xe2x80x2 and 222xe2x80x2 extend under gate 18 (i.e., into the transistor channel). The anneal step may be achieved using various parameters, such as a rapid thermal anneal (xe2x80x9cRTAxe2x80x9d) at a temperature on the order of 900xc2x0 C. After the anneal, a second insulating layer 24 is formed. Typically, second insulating layer 24 is an oxide layer deposited as a conformal layer, which may be accomplished by way of example using a TEOS approach as known in the art. Such an approach commonly uses a deposition temperature on the order of 600 to 650xc2x0 C. Lastly, a third insulating layer 26 is formed. Typically, third insulating layer 26 is a nitride layer, also deposited as a conformal layer. Such an approach commonly uses a deposition temperature on the order of 700 to 750xc2x0 C.
FIG. 1c illustrates device 10 after the steps of FIG. 1b, and additionally in FIG. 1c an etch is performed with respect to nitride layer 26, and insulating layers 20 and 24; the resulting portions of these layers are labeled 26xe2x80x2, 20xe2x80x2, and 24xe2x80x2, respectively, so as to distinguish them from their form in FIG. 1b. As a result of the etch, the combination of portions 26xe2x80x2, 20xe2x80x2, and 24xe2x80x2 form sidewall spacers along the sidewalls of gate 18. The etch also exposes the upper surface of n-type well 12xe2x80x2 beyond the area covered by the sidewall spacers and gate stack 14. Once the sidewall spacers of FIG. 1c are formed, then a p-type dopant (e.g., boron) is implanted into device 10. This p-type implant may be achieved using various process parameters. The p-type implant forms deep source/drain regions 281 and 282 self-aligned with respect to the sidewall spacers of gate 18.
FIG. 1d illustrates device 10 after the steps of FIG. 1c, and additionally in FIG. 1d a second anneal is performed. The second annealing step activates the dopants implanted to form deep source/drain regions 281 and 282 shown in FIG. 1c. In response to the anneal, the dopants in deep source/drain regions 281 and 282 of FIG. 1c midgrate laterally and they also further combine with source/drain extensions 221xe2x80x2 and 222xe2x80x2. For the sake of distinction, the laterally-migrated deep source/drain regions in FIG. 1d are labeled 281xe2x80x2 and 282xe2x80x2. The second anneal step may be achieved using various parameters, such as an RTA on the order of 950 to 1100xc2x0 C. and for a desirable amount of time. Lastly, following the preceding steps, various other steps may be taken to form other aspects with respect to the NMOS transistor, including other layers for connectivity and the like.
While device 10 performs adequately in many circuits and applications, it has been observed in connection with the present inventive embodiments that device 10 may provide certain drawbacks. For example, the present inventors have observed increased electrical resistance relating to the transistor channel. Such resistance undesirably reduces the transistor drive current and, thus, can be a drawback for various applications. The present inventors have therefore studied the dopant profile of source/drain extensions 221xe2x80x2 and 222xe2x80x2 to determine if the profile may be altered to improve the resistance characteristics of those regions and thereby improve the transistor drive current. In addition, the present inventors have examined the above-described process flow to determine if it may be improved.
In connection with a further analysis of the prior art, FIG. 2 illustrates a plot 30 of the dopant profile for either of source/drain extensions 221xe2x80x2 and 222xe2x80x2 of the prior art device 10. Plot 30 is not drawn to precise scale but instead is sketched to illustrate various aspects now described. Looking to FIG. 2 in greater detail, its vertical axis identifies dopant concentration which begins at a zero concentration point y0 and increases in a logarithmic fashion up the vertical axis, and its horizontal axis illustrates depth into n-type well 12xe2x80x2, starting at its surface x0 and moving into n-type well 12xe2x80x2 toward the right along the horizontal axis. Generally, therefore, it may be seen from plot 30 that dopant concentration is larger toward the surface of n-type well 12xe2x80x2 and then decreases at greater depths within n-type well 12xe2x80x2. However, two aspects are illustrated by plot 30 that cause drawbacks and that are also later described in connection with the preferred embodiments. As a first observation, note that at depth x0 the dopant concentration is at y1, whereas at depth x1 the dopant concentration is larger at a value y2; in other words, at or just below the surface (i.e., at or just past x0), there is actually a reduced amount of dopant concentration y1 as opposed to the dopant concentration y2 existing at depth x1. Such a result is generally undesirable because it gives rise to less than optimal performance, such as increasing the resistance of the source/drain extensions and thereby reducing drive current. As a second observation, note that after the dopant concentration begins to fall at depths greater than x1, the curve is fairly smooth from x1 to x2; however, at x2, the slope of the curve flattens, thereby creating an area in the curve which is sometimes referred to as the tail. In other words, if the curve were to maintain its drop-off after x2, then the concentration would fall to a negligible value at approximately x3, as shown by a theoretical dotted line extending to x3. Instead, however, the tail indicates that dopant concentration remains non-negligible at a depth greater than x3, that is, the dopants extend at least to x4. This additional dopant concentration toward x4 also may produce undesirable operation of the transistor. For example, this dopant concentration may permit current leakage between respective source/drain extensions at a region that is relatively deep in the well, that is, below the intended area of the transistor channel.
In view of the above, there arises a need to address the drawbacks of the prior art, as is achieved by the preferred embodiments described below.
In the preferred embodiment, there is a method of forming an integrated circuit device comprising a substrate. The method comprises the step of first, forming a gate stack in a fixed relationship to the substrate, the gate stack comprising a gate having sidewalls. The method further comprises the step of second, implanting source/drain extensions into the substrate and self-aligned relative to the gate stack. The method further comprises the steps of third, forming a first sidewall-forming layer in a fixed relationship to the sidewalls and forming a second sidewall-forming layer in a fixed relationship to the sidewalls. The step of forming a second sidewall-forming layer comprises depositing the second sidewall-forming layer at a temperature equal to or greater than approximately 850xc2x0 C. The method further comprises the step of fourth, implanting deep source/drain regions into the substrate and self-aligned relative to the gate stack and the first and second sidewall-forming layers. Other aspects are also disclosed and claimed.